Organic light emitting diode display and method for driving the same

ABSTRACT

Disclosed is an organic light emitting diode (OLED) display that includes a display panel including a plurality of gate lines and a plurality of data lines crossing each other to define a plurality of pixels, each pixel including a driving transistor, a switching transistor, an OLED and a storage capacitor; a timing controller that receives pixel data of an input image and timing signals and time-divides a period of one frame into at least a driving sub-frame and a compensation sub-frame based on one or more of the timing signals; and a display panel driver that converts the pixel data into data voltages and supplies the data voltages to the plurality of data lines during the driving sub-frame, and that adjusts compensation gray levels of the plurality of pixels or compensation duties of the plurality of pixels based on a luminance map, which contains information on a luminance deviation for each pixel with respect to a same gray level, during the compensation sub-frame.

This application claims the benefit of Korea Patent Application No.10-2015-0190434 filed on Dec. 30, 2015, which is incorporated herein byreference for all purposes as if fully set forth herein.

BACKGROUND

Field of the Invention

The present disclosure relates to an organic light emitting diodedisplay and a method for driving the same.

Discussion of the Related Art

An organic light emitting diode (OLED) display includes a plurality oforganic light emitting diodes (OLEDs) capable of emitting light bythemselves and has many advantages, such as fast response time, highemission efficiency, high luminance, wide viewing angle, and the like.

An OLED serving as a self-emitting element includes an anode electrode,a cathode electrode, and an organic compound layer between the anodeelectrode and the cathode electrode. The organic compound layertypically includes a hole injection layer HIL, a hole transport layerHTL, an emission layer EML, an electron transport layer ETL, and anelectron injection layer EIL. When a driving voltage is applied to theanode electrode and the cathode electrode, holes passing through thehole transport layer HTL and electrons passing through the electrontransport layer ETL move to the emission layer EML and form excitons. Asa result, the emission layer EML generates visible light.

An OLED display includes a plurality of pixels, each including an OLEDin a matrix and adjusts the luminance of the pixel based on a gray scaleof video data. Each pixel includes a driving element, for example, adriving thin film transistor (TFT) for controlling an amount of drivingcurrent flowing in the OLED depending on a voltage applied between agate electrode and a source electrode of the driving TFT. The electricalcharacteristics of the OLED and the driving TFT may vary depending ontheir operation temperatures or amounts of deterioration. For example,an operating voltage of the OLED, a threshold voltage and a mobility ofthe driving TFT, etc. may change because these elements deteriorate astheir driving times increase. Further, the electrical characteristics ofthese elements may vary due to variations in manufacturing processes.These variations in the electrical characteristics of the OLEDs and/orthe driving TFTs of the pixels may result in difference in the luminanceof the pixels with respect to the same video data, thereby making itchallenging to display a desired image.

Also, an IR drop may be generated in the OLED display due to the lineresistance of a high potential power source. Thus, a magnitude of a highpotential power voltage applied to each pixel line, which is typicallyconnected to a plurality of pixels in a horizontal direction, on thedisplay panel may vary depending on a separation distance between thepixel line and the high potential power source and result in deviationin the luminance of the pixel line, thereby also making it challengingto display a desired image.

SUMMARY

Accordingly, the present disclosure is directed to an organic lightemitting diode display and a method for driving the same. thatsubstantially obviate one or more problems due to limitations anddisadvantages of the related art.

An advantage of the present disclosure is to provide an organic lightemitting display device with improved display images.

Additional advantages and features of the present disclosure will be setforth in part in the description which follows and in part will becomeapparent to those having ordinary skill in the art upon examination ofthe following or may be learned from practice of the disclosure. Theobjectives and other advantages of the disclosure may be realized andattained by the structure particularly pointed out in the writtendescription and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purposeof the disclosure, as embodied and broadly described herein, an organiclight emitting diode (OLED) display may, for example, include a displaypanel including a plurality of gate lines and a plurality of data linescrossing each other to define a plurality of pixels, each pixelincluding a driving transistor, a switching transistor, an OLED and astorage capacitor; a timing controller that receives pixel data of aninput image and timing signals and time-divides a period of one frameinto at least a driving sub-frame and a compensation sub-frame based onone or more of the timing signals; and a display panel driver thatconverts the pixel data into data voltages and supplies the datavoltages to the plurality of data lines during the driving sub-frame,and that adjusts compensation gray levels of the plurality of pixels orcompensation duties of the plurality of pixels based on a luminance map,which contains information on a luminance deviation for each pixel withrespect to a same gray level, during the compensation sub-frame.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description serve to explain the principles of theinvention. In the drawings:

FIGS. 1 and 2 illustrate an organic light emitting diode (OLED) displayaccording to an exemplary embodiment of the invention;

FIG. 3 illustrates that one frame is time-divided into a drivingsub-frame and a compensation sub-frame in accordance with an exemplaryembodiment of the invention;

FIGS. 4A and 4B illustrate an equivalent circuit of a pixel applied toan exemplary embodiment of the invention;

FIG. 5 illustrates an example of adjusting compensation gray levels ofpixels during a compensation sub-frame to compensate for a luminancedeviation of each pixel;

FIG. 6 illustrates an example of adjusting compensation duties of pixelsduring a compensation sub-frame to compensate for a luminance deviationof each pixel;

FIGS. 7 and 8 illustrate operating characteristics of a driving thinfilm transistor (TFT) in accordance with a high potential power source;

FIG. 9 illustrates that a luminance deviation is generated due to an IRdrop depending on a location of a display panel;

FIG. 10 illustrates an example of compensating for a luminance deviationbetween pixel lines resulting from an IR drop through a compensationsub-frame when a high potential power source exists in an active regionof a driving TFT;

FIG. 11 illustrates a luminance implemented in accordance with acompensation gray level;

FIG. 12 illustrates an example of adjusting compensation gray levels ofpixels during a compensation sub-frame, so as to compensate for aluminance deviation of each display line;

FIG. 13 illustrates an example of adjusting compensation duties ofpixels during a compensation sub-frame, so as to compensate for aluminance deviation of each display line;

FIG. 14 illustrates an example where one frame includes a plurality ofdriving sub-frames to increase or maximize a gray level representationperformance; and

FIGS. 15 and 16 illustrate a number of representable gray levels and agray level curve when a gray level representation performance increasesby 15%.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to embodiments of the invention,examples of which are illustrated in the accompanying drawings. Whereverpossible, the same reference numbers will be used throughout thedrawings to refer to the same or like parts. Detailed description ofknown arts will be omitted if it is determined that the arts can misleadthe embodiments of the invention.

FIGS. 1 and 2 illustrate an organic light emitting diode (OLED) displayaccording to an exemplary embodiment of the invention. FIG. 3illustrates that one frame is time-divided into a driving sub-frame anda compensation sub-frame in accordance with an exemplary embodiment ofthe invention.

Referring to FIGS. 1 and 2, the OLED display according to an exemplaryembodiment of the invention includes a display panel 10, a display paneldriver for applying pixel data of an input image to an array of pixelsin the display panel 10, a timing controller 11 for controlling thedisplay panel driver, and a memory 14 for storing a luminance map. Thedisplay panel driver includes a data driver 12 and a gate driver 13.

On the pixel array of the display panel 10, a plurality of data lines 15and a plurality of gate lines 16 cross each other. The pixel array ofthe display panel 10 includes pixels PXL that are arranged in a matrixand display an input image. Each pixel PXL may be one of a red (R)pixel, a green (G) pixel, a blue (B) pixel, and a white (W) pixel. Eachpixel PXL may include a plurality of thin film transistors (TFTs), anorganic light emitting diode (OLED) and a capacitor. Each gate line 16may include a scan control line as illustrated in FIG. 4A, or mayfurther include an emission control line in addition to the scan controlline as illustrated in FIG. 4B.

The timing controller 11 receives pixel data RGB of an input image andtiming signals Vsync, Hsync, DE, and DCLK from a host system (notshown). As illustrated in FIG. 3, the timing controller 11 time-dividesone frame into at least a driving sub-frame DSF and a compensationsub-frame CSF based on one or more of the timing signals Vsync, Hsync,DE, and DCLK. The driving sub-frame DSF is used to apply the pixel dataRGB of the input image to the pixels PXL, and the compensation sub-frameCSF is used to compensate for a luminance deviation of each pixel.During the compensation sub-frame CSF, the timing controller 11 controlsan operation of the display panel driver and adjusts compensation graylevels of the pixels PXL or compensation duties of the pixels PXL,thereby to compensate for a luminance deviation of each pixel. Thetiming controller 11 may refer to the luminance map stored in the memory14 so as to adjust compensation gray levels of the pixels PXL orcompensation duties of the pixels PXL.

The timing controller 11 produces a source timing control signal DDC forcontrolling an operation timing of the data driver 12 and a gate timingcontrol signal GDC for controlling an operation timing of the gatedriver 13 during each of the driving sub-frame DSF and the compensationsub-frame CSF based on one or more of the timing signals Vsync, Hsync,DE, and DCLK.

The timing controller 11 may supply the pixel data RGB of the inputimage to the data driver 12 during the driving sub-frame DSF. The timingcontroller 11 may supply compensation data for compensating for aluminance deviation of the pixels PXL to the data driver 12 during thecompensation sub-frame CSF, thereby adjusting a compensation gray levelon a per pixel basis. Further, the timing controller 11 may supply blackdata for compensating for a luminance deviation of the pixels PXL to thedata driver 12 during the compensation sub-frame CSF, thereby adjustinga compensation gray level on a per pixel basis. Further, the timingcontroller 11 may control an operation of the gate driver 13 during thecompensation sub-frame CSF and control a production timing of anemission control signal, thereby adjusting a compensation duty forcompensating for a luminance deviation of the pixels PXL on a per pixelbasis.

The timing controller 11 may supply compensation data for compensatingfor a luminance deviation of the pixel lines resulting from an IR dropto the data driver 12 during the compensation sub-frame CSF, therebyadditionally adjusting a compensation gray level on a per pixel linebasis. Further, the timing controller 11 may supply black data forcompensating for a luminance deviation of the pixel lines resulting froman IR drop to the data driver 12 during the compensation sub-frame CSF,thereby additionally adjusting a compensation gray level on a per pixelline basis. Further, the timing controller 11 may control an operationof the gate driver 13 during the compensation sub-frame CSF and controla production timing of an emission control signal, thereby additionallyadjusting a compensation duty for compensating for a luminance deviationof the pixel lines on a per pixel line basis.

During the driving sub-frame DSF, the data driver 12 may convert thepixel data RGB of the input image into data voltages in response to thesource timing control signal DDC and output the data voltages to thedata lines 15. During the compensation sub-frame CSF, the data driver 12may convert compensation data for compensating for a luminance deviationinto compensation voltages in response to the source timing controlsignal DDC and output the compensation voltages to the data lines 15.During the compensation sub-frame CSF, the data driver 12 may convertblack data for compensating for a luminance deviation into blackvoltages in response to the source timing control signal DDC and outputthe black voltages to the data lines 15.

In the embodiment disclosed herein, the data voltages and thecompensation voltages are selected within a voltage range capable ofcausing a current to flow between a drain electrode and a sourceelectrode of a driving TFT and increase in proportion to gray levels. Onthe other hand, the black voltages indicate a voltage range that causesa current not to flow between the drain electrode and the sourceelectrode of the driving TFT. Controlling compensation gray levels on aper pixel basis or a per pixel line basis may be implemented bycontrolling a size of the compensation data on a per pixel basis or aper pixel line basis during a compensation sub-frame. Controllingcompensation duties on a per pixel basis or a per pixel line basis maybe implemented by controlling an application timing of the black data ona per pixel basis or a per pixel line basis during the compensationsub-frame.

During each of the driving sub-frame DSF and the compensation sub-frameCSF, the gate driver 13 may produce a scan control signal in response tothe gate timing control signal GDC and supply the scan control signal tothe gate lines 16 (more specifically, scan control lines) in a linesequential manner. During the compensation sub-frame CSF, the gatedriver 13 may additionally produce an emission control signal inresponse to the gate timing control signal GDC and supply the emissioncontrol signal to the gate lines 16 (more specifically, emission controllines).

In the embodiment disclosed herein, the scan control line may becommonly connected to the pixels PXL on the same pixel line. On theother hand, the emission control lines may be individually connected toall of the pixels PXL, so that compensation duties are controlled on aper pixel basis. Further, the emission control lines may be commonlyconnected to the pixels PXL on the same pixel line, so that compensationduties are controlled on a per pixel line basis. Controllingcompensation duties on a per pixel basis or a per pixel line basis maybe implemented by controlling an application timing of the emissioncontrol signal on a per pixel basis or a per pixel line basis during thecompensation sub-frame.

The memory 14 stores a luminance map that contains information on aluminance deviation for each pixel corresponding to the same gray level.The luminance map may be previously measured using a luminance measuringinstrument, etc. during a shipment step and may be stored. The luminancemap may be updated based on a result of sensing changes in electricalcharacteristics of the driving TFT and the OLED after shipment. Anupdate of the luminance map may be performed at predetermined intervals.The luminance map may further include information on a luminancedeviation of each pixel line depending on a separation distance betweenthe pixel line and the high potential power source.

FIGS. 4A and 4B illustrate an equivalent circuit of a pixel according toan embodiment of the present invention.

Referring to FIG. 4A, a pixel PXL according to an embodiment of thepresent invention may include an OLED, a driving TFT DT, a switching TFTST, a storage capacitor Cst, and the like. A pixel structure illustratedin FIG. 4A may be applied to both a compensation method of FIG. 5 foradjusting a compensation gray level during the compensation sub-frameCSF and a compensation method of FIG. 6 for adjusting a compensationduty during the compensation sub-frame CSF.

An OLED has a structure in which organic compound layers, such as a holeinjection layer HIL, a hole transport layer HTL, an emission layer EML,an electron transport layer ETL, and an electron injection layer EIL,are stacked. The OLED generates light when electrons and holes arecombined in the emission layer EML. An anode electrode of the OLED isconnected to a source node Ns, and a cathode electrode of the OLED isconnected to a low potential power source EVSS.

The driving TFT DT is a driving element that makes the OLED emit lightby applying a drain-to-source current of the driving TFT DT to the OLED.The driving TFT DT is connected between a high potential power sourceEVDD and the OLED and may produce the drain-to-source current inproportion to a data voltage Vdata or a compensation voltage applied toa gate node Ng. When a black voltage is applied to the gate node Ng ofthe driving TFT DT, the drain-to-source current may not be generated. Agate electrode of the driving TFT DT may be connected to the gate nodeNg, and a drain electrode of the driving TFT DT may be connected to thehigh potential power source EVDD. A source electrode of the driving TFTDT may be connected to the source node Ns.

The switching TFT ST is turned on in response to a scan control signalSP from the scan control line 16. The switching TFT ST may supply thedata voltage Vdata, the compensation voltage, or the black voltage tothe gate node Ng in response to the scan control signal SP. A gateelectrode of the switching TFT ST may be connected to the scan controlline 16, and a drain electrode of the switching TFT ST may be connectedto the data line 15. A source electrode of the switching TFT ST may beconnected to the gate node Ng.

The storage capacitor Cst holds a gate-to-source voltage of the drivingTFT DT for a predetermined period of time. The storage capacitor Cst isconnected between the gate node Ng and the source node Ns of the drivingTFT DT and holds a voltage applied to the gate node Ng.

Referring to FIG. 4B, a pixel PXL according to an embodiment of thepresent invention may include an OLED, a driving TFT DT, a firstswitching TFT ST1, a second switching TFT ST2, a storage capacitor Cst,and the like. A pixel structure illustrated in FIG. 4B may be applied toboth a compensation method of FIG. 5 for adjusting a compensation graylevel during the compensation sub-frame CSF and a compensation method ofFIG. 6 for adjusting a compensation duty during the compensationsub-frame CSF.

Since the OLED, the driving TFT DT, and the storage capacitor Cst inFIG. 4B are substantially the same as those illustrated in FIG. 4A, aduplicative description thereof may be omitted.

The first switching TFT ST1 is turned on in response to a scan controlsignal SP from a scan control line 16A. The first switching TFT ST1 maysupply a data voltage Vdata or a compensation voltage to a gate node Ngin response to the scan control signal SP. A gate electrode of the firstswitching TFT ST1 may be connected to the scan control line 16A, and adrain electrode of the first switching TFT ST1 may be connected to adata line 15. A source electrode of the first switching TFT ST1 may beconnected to the gate node Ng.

The second switching TFT ST2 is turned on in response to an emissioncontrol signal EP from an emission control line 16B. The secondswitching TFT ST2 connects a low potential power source EVSS to the gatenode Ng in response to the emission control signal EP. A gate electrodeof second switching TFT ST2 may be connected to the emission controlline 16B, and a source electrode of the second switching TFT ST2 may beconnected to the low potential power source EVSS. A drain electrode ofthe second switching TFT ST2 may be connected to the gate node Ng. Whenthe low potential power source EVSS is connected to the gate node Ng,the data voltage Vdata, that has been stored in the gate node Ng, isdischarged up to the low potential power source EVSS. As a result, thedriving TFT DT may not produce a drain-to-source current. The drivingTFT DT may produce the drain-to-source current in proportion to a datavoltage Vdata or a compensation voltage applied to the gate node Ng.

FIG. 5 illustrates an example of adjusting compensation gray levels ofpixels during a compensation sub-frame to compensate for a luminancedeviation of each pixel. More specifically, FIG. 5 illustrates that eachof pixel data and compensation data is implemented with 8-bit data byway of example.

Referring to FIG. 5, the embodiment of the invention may control anoperation of the display panel driver with reference to a luminance mapshown in (A) of FIG. 5 during a compensation sub-frame CSF and adjustcompensation gray levels of the pixels PXL as shown in (B) of FIG. 5during the compensation sub-frame CSF, thereby compensating for aluminance deviation of each pixel as shown in (C) of FIG. 5.

More specifically, in the luminance map shown in (A) of FIG. 5, pixelsP1, P7, P10, and P16 each have a luminance of 100 nit; pixels P2 and P12each have a luminance of 70 nit; pixels P3, P9, and P15 each have aluminance of 85 nit; pixels P4 and P13 each have a luminance of 95 nit;pixels P5 and P14 each have a luminance of 75 nit; a pixel P6 has aluminance of 90 nit; and pixels P8 and P11 each have a luminance of 80nit.

The embodiment of the invention may apply pixel data to all of thepixels P1 to P16 during a driving sub-frame DSF. The embodiment of theinvention describes that the pixel data is applied to all of the pixelsP1 to P16 at a maximum gray level of 255, but is not limited thereto.For example, the pixel data may be applied to at least some of thepixels P1 to P16 at different gray levels.

In this instance, the embodiment of the invention may apply compensationdata of gray level “200” to each of the pixels P1, P7, P10, and P16,apply compensation data of gray level “255” to each of the pixels P2 andP12, apply compensation data of gray level “255” to each of the pixelsP3, P9, and P15, apply compensation data of gray level “205” to each ofthe pixels P4 and P13, apply compensation data of gray level “245” toeach of the pixels P5 and P14, apply compensation data of gray level“215” to the pixel P6, and apply compensation data of gray level “235”to each of the pixels P8 and P11 with reference to the luminance mapshown in (A) of FIG. 5 during the compensation sub-frame CSF.

When the luminances of first and second pixels corresponding to the samegray level on the luminance map are different from each other asdescribed above (for example, when a luminance of the first pixel isless than a luminance of the second pixel), the embodiment of theinvention adjusts a compensation gray level of the first pixel to begreater than a compensation gray level of the second pixel during thecompensation sub-frame CSF, thereby compensating for the luminances ofall of the pixels P1 to P16 using a minimum luminance of the luminancemap as shown in (C) of FIG. 5. The embodiment of the invention mayincrease a compensation luminance using a method of increasing a gammapower voltage applied to a gamma string of a data driving circuit, etc.as shown in (D) of FIG. 5.

FIG. 6 illustrates an example of adjusting compensation duties of pixelsduring a compensation sub-frame CSF to compensate for a luminancedeviation of each pixel. More specifically, FIG. 6 illustrates that eachof pixel data and compensation data is implemented with 8-bit data byway of example.

Referring to FIG. 6, the embodiment of the invention may control anoperation of the display panel driver with reference to a luminance mapshown in (A) of FIG. 6 during a compensation sub-frame CSF and adjustcompensation gray levels of the pixels PXL as shown in (B) of FIG. 6during the compensation sub-frame CSF, thereby compensating for aluminance deviation of each pixel as shown in (C) of FIG. 6.

More specifically, in the luminance map shown in (A) of FIG. 6, pixelsP1, P7, P10, and P16 each have a luminance of 100 nit; pixels P2 and P12each have a luminance of 70 nit; pixels P3, P9, and P15 each have aluminance of 85 nit; pixels P4 and P13 each have a luminance of 95 nit;pixels P5 and P14 each have a luminance of 75 nit; a pixel P6 has aluminance of 90 nit; and pixels P8 and P11 each have a luminance of 80nit.

The embodiment of the invention may apply pixel data to all of thepixels P1 to P16 during a driving sub-frame DSF. The embodiment of theinvention describes that the pixel data is applied to all of the pixelsP1 to P16 at a maximum gray level of 255, but is not limited thereto.For example, the pixel data may be applied to at least some of thepixels P1 to P16 at different gray levels.

In this instance, the embodiment of the invention may control anemission duty of each of the pixels P1, P7, P10, and P16 based on pixeldata of gray level “255” to a first value D100, control an emission dutyof each of the pixels P2 and P12 based on pixel data of gray level “255”to a second value D70, control an emission duty of each of the pixelsP3, P9, and P15 based on pixel data of gray level “255” to a third valueD85, control an emission duty of each of the pixels P4 and P13 based onpixel data of gray level “255” to a fourth value D95, control anemission duty of each of the pixels P5 and P14 based on pixel data ofgray level “255” to a fifth value D75, control an emission duty of thepixel P6 based on pixel data of gray level “255” to a sixth value D90,and control an emission duty of each of the pixels P8 and P11 based onpixel data of gray level “255” to a seventh value D80 with reference tothe luminance map shown in (A) of FIG. 6 during the compensationsub-frame CSF. The emission duty gradually shortens in the order of thesecond value D70, the fifth value D75, the seventh value D80, the thirdvalue D85, the sixth value D90, the fourth value D95, and the firstvalue D100. In other words, the emission duty gradually lengthens in theorder of the first value D100, the fourth value D95, the sixth valueD90, the third value D85, the seventh value D80, the fifth value D75,and the second value D70.

When the luminances of first and second pixels corresponding to the samegray level on the luminance map are different from each other asdescribed above (for example, when a luminance of the first pixel isless than a luminance of the second pixel), the embodiment of theinvention adjusts a compensation duty of the first pixel to be longerthan a compensation duty of the second pixel during the compensationsub-frame CSF, thereby compensating for the luminances of all of thepixels P1 to P16 using a minimum luminance of the luminance map as shownin (C) of FIG. 6. The embodiment of the invention may increase acompensation luminance using a method of increasing a gamma powervoltage applied to a gamma string of a data driving circuit, etc. asshown in (D) of FIG. 6.

FIGS. 7 and 8 illustrate operating characteristics of a driving TFTconnected to a high potential power source. FIG. 9 illustrates that aluminance deviation is generated due to an IR drop depending on alocation of a display panel. FIG. 10 illustrates an example ofcompensating for a luminance deviation between pixel lines resultingfrom an IR drop during a compensation sub-frame when a high potentialpower source exists in an active region of a driving TFT.

Referring to FIG. 7, an OLED included in each pixel PXL receives adrain-to-source current Ids of a driving TFT DT and emits light. Anamount of light emitted by the OLED is proportional to a magnitude ofthe drain-to-source current Ids. The drain-to-source current Ids isdetermined by a difference Vgs between a voltage applied to a gateelectrode G of the driving TFT DT and a voltage applied to a sourceelectrode S of the driving TFT DT. In each pixel PXL, a high potentialpower source EVDD is applied to a drain electrode D of the driving TFTDT, and a low potential power source EVSS is applied to a cathodeelectrode of the OLED.

The high potential power source EVDD may generally exist in a saturationregion in Vds-Ids plane shown in FIG. 8. The saturation region indicatesa voltage region, in which the drain-to-source current Ids does notsubstantially change in spite of changes in a drain-to-source voltageVds of the driving TFT DT. When a power voltage is set in the saturationregion as in a high potential power source EVDD1 shown in FIG. 8, thedriving TFT DT is advantageous in operational stability. However, thedriving TFT DT has a disadvantage of an increase in power consumptionbecause of the high power voltage.

Hence, the embodiment of the invention is to reduce the power voltagefor reducing power consumption, so that a voltage level of the highpotential power source EVDD exists in an active region in the Vds-Idsplane shown in FIG. 8. In the embodiment disclosed herein, the activeregion indicates a voltage region, in which the drain-to-source currentIds changes depending on changes in the drain-to-source voltage Vds ofthe driving TFT DT.

However, when the power voltage is set in the active region as in theembodiment of the invention, which means the drain-to-source current Idschanges depending on a magnitude (i.e., the drain-to-source voltage Vdsof the driving TFT DT) of the high potential power source EVDD in theactive region as shown in FIG. 8, the embodiment of the invention ispreferred to prepare a measure to compensate for a luminance deviationresulting from an IR drop.

The IR drop of the display panel 10 is generated by a line resistance ofthe high potential power source EVDD. As shown in FIG. 9, as the highpotential power source EVDD is distanced away from the pixel line, anamount of IR drop increases. Because an increase in IR drop reduces amagnitude of the high potential power source EVDD applied to the pixelPXL, the luminance is reduced, and a line dim may be generated in thedisplay panel 10 on a per pixel line basis.

In order to remove a luminance deviation of each pixel line resultingfrom such an IR drop, the embodiment of the invention previously storesa luminance deviation of each pixel line in a luminance map and controlsan operation of a display panel driver during a compensation sub-frameCSF shown in FIG. 10. As a result, the embodiment of the invention canadjust compensation gray levels or compensation duties of the pixels PXLand can additionally compensate for a luminance deviation of each pixelline. As shown in FIG. 10, because the high potential power source EVDDexists in the active region, the power voltage is reduced from V1 to V2,and the power consumption is reduced by a reduction amount of the powervoltage.

FIG. 11 illustrates a luminance map implemented in accordance withcompensation gray levels. FIG. 12 illustrates an example of adjustingcompensation gray levels of pixels during a compensation sub-frame, soas to compensate for a luminance deviation of each display line. FIG. 13illustrates an example of adjusting compensation duties of pixels duringa compensation sub-frame, so as to compensate for a luminance deviationof each display line.

Referring to FIGS. 11 and 12, when there are first and second pixellines corresponding to the same gray level on the luminance map and aluminance of the first pixel line is less than a luminance of the secondpixel line, the embodiment of the invention may additionally adjust acompensation gray level of the first pixel line to be greater than acompensation gray level of the second pixel line during the compensationsub-frame CSF so as to compensate for a luminance deviation of eachpixel line resulting from an IR drop.

For example, when a driving sub-frame DSF and a compensation sub-frameCSF of one frame is set to a ratio of 6:4, the embodiment of theinvention applies compensation data of gray level “200” to pixels PXL ofa pixel line L12 closest to the high potential power source EVDD andapplies compensation data of gray level “255” to pixels PXL of a pixelline L1 farthest from the high potential power source EVDD during thecompensation sub-frame CSF. Because a separation distance between thepixel line and the high potential power source EVDD gradually increasesas the pixel line changes from L11 to L2, the embodiment of theinvention gradually increases a gray level of compensation data. Thus,the embodiment of the invention can reduce a luminance deviation of eachpixel line resulting from an IR drop by applying compensation data ofdifferent gray levels to the pixel lines.

Referring to FIG. 13, when there are first and second pixel linescorresponding to the same gray level on the luminance map and aluminance of the first pixel line is less than a luminance of the secondpixel line, the embodiment of the invention may additionally adjust acompensation duty of the first pixel line to be greater than acompensation duty of the second pixel line during the compensationsub-frame CSF, so as to compensate for a luminance deviation of eachpixel line resulting from an IR drop.

For example, when a driving sub-frame DSF and a compensation sub-frameCSF of one frame is set to a ratio of 6:4, the embodiment of theinvention controls an emission duty of pixels PXL on a pixel line L12closest to the high potential power source EVDD to D47.2 and controls anemission duty of pixels PXL on a pixel line L1 farthest from the highpotential power source EVDD to D100 during the compensation sub-frameCSF. Because a separation distance between the pixel line and the highpotential power source EVDD gradually increases as the pixel linechanges from L11 to L2, the embodiment of the invention graduallyincreases a compensation duty. Thus, the embodiment of the invention canreduce a luminance deviation of each pixel line resulting from an IRdrop by applying different compensation duties to the pixel lines.

FIG. 14 illustrates an example where one frame includes a plurality ofdriving sub-frames to increase a gray level representation performanceFIGS. 15 and 16 illustrate a number of representable gray levels and agray level curve when a gray level representation performance increasesby 15%.

Referring to FIG. 14, the embodiment of the invention assigns aplurality of driving sub-frames DSF1 and DSF2, in which pixel data isapplied, to one frame, and thus can increase a number of representablegray levels with respect to the pixel data and increase a gray levelrepresentation performance.

When pixel data is 8-bit data, the number of representable gray levelsdepending on the number ‘k’ of driving sub-frames is “256*(2^(k)−1)”.For example, as shown in FIG. 14, the number ‘k’ of driving sub-framesis two, the number of representable gray levels is 256*3 (DSF1, DSF2=on,on) (DSF1, DSF2=on, off) (DSF1, DSF2=off, on).

In this instance, as shown in FIG. 15, with gray level representationperformance increased by 15%, when gray levels are mapped at a luminanceclosest to gray level “295” among 768 representable gray levels, a graylevel curve shown in FIG. 16, in which an average error of each graylevel is 0.77%, may be obtained. As a result, the embodiment of theinvention can increase or maximize gray level representation performanceby controlling a number of driving sub-frames in one frame.

As described above, an embodiment of the invention may efficientlycompensate for a luminance deviation of each pixel by adjustingcompensation gray levels or compensation duties of pixels through acompensation sub-frame included in one frame.

Also, an embodiment of the invention may reduce a power voltage level sothat a voltage level of a high potential power source exists in anactive region of a Vds-Ids plane, and thus can reduce power consumption.The embodiment of the invention may adjust compensation gray levels orcompensation duties of pixels through a compensation sub-frame includedin one frame, and thus may additionally compensate for a luminancedeviation of each pixel line resulting from an IR drop.

Moreover, an embodiment of the invention may increase a number ofrepresentable gray levels with respect to pixel data and increase aluminance representation performance by assigning a plurality of drivingsub-frames, in which pixel data is applied, to one frame.

Although embodiments have been described with reference to a number ofillustrative embodiments thereof, it should be understood that numerousother modifications and embodiments can be devised by those skilled inthe art that will fall within the scope of the principles of thisdisclosure. More particularly, various variations and modifications arepossible in the component parts and/or arrangements of the subjectcombination arrangement within the scope of the disclosure, the drawingsand the appended claims. In addition to variations and modifications inthe component parts and/or arrangements, alternative uses will also beapparent to those skilled in the art.

What is claimed is:
 1. An organic light emitting diode (OLED) displaycomprising: a display panel including a plurality of gate lines and aplurality of data lines crossing each other to define a plurality ofpixels, each pixel including a driving transistor, a switchingtransistor, an OLED and a storage capacitor; a timing controller thatreceives pixel data of an input image and timing signals andtime-divides a period of one frame into at least a driving sub-frame anda compensation sub-frame based on one or more of the timing signals; anda display panel driver that converts the pixel data into data voltagesand supplies the data voltages to the plurality of data lines during thedriving sub-frame, and that adjusts compensation gray levels of theplurality of pixels or compensation duties of the plurality of pixelsbased on a luminance map, which contains information on a luminancedeviation for each pixel with respect to a same gray level, during thecompensation sub-frame.
 2. The OLED of claim 1, further comprising amemory that stores the luminance map, wherein the timing controllerincludes the luminance map, and wherein the display panel driverincludes a data driver and a gate driver.
 3. The OLED of claim 1,wherein the timing controller generates compensation data based on thepixel data and the luminance map, and wherein the display panel driverconverts the compensation data into compensation voltages and suppliesthe compensation voltages to the plurality of data lines during thecompensation sub-frame.
 4. The OLED of claim 3, wherein the compensationvoltages adjust the compensation gray levels of the plurality of pixelson a per pixel basis or a per pixel line basis.
 5. The OLED of claim 4,wherein the compensation voltages are within a range of voltages thatcauses a current to flow between source and drain electrodes of thedriving transistor.
 6. The OLED of claim 1, wherein the timingcontroller generates black data based on the pixel data and theluminance map, and wherein the display panel driver converts the blackdata into black voltages and supplies the black voltages to theplurality of data lines during the compensation sub-frame.
 7. The OLEDof claim 6, wherein the black voltages adjust the compensation graylevels of the plurality of pixels on a per pixel basis or a per pixelline basis.
 8. The OLED of claim 7, wherein the black voltages arewithin a range of voltages that causes a current not to flow betweensource and drain electrodes of the driving transistor.
 9. The OLED ofclaim 1, wherein each gate line includes a scan control line and anemission control line.
 10. The OLED of claim 9, wherein the emissioncontrol line is connected to a second switching transistor, and whereinwhen the second switching transistor is turned on in response to anemission control signal, a low potential power source is electricallyconnected to an electrode of the storage capacitor.
 11. The OLED ofclaim 10, wherein the display panel driver adjusts compensation dutiesof the plurality of pixels by controlling a production timing of theemission control signal supplied to the emission control line of eachgate line on a per pixel basis or a per pixel line basis.
 12. The OLEDof claim 11, wherein emission control lines of the plurality of gatelines are individually, electrically connected to the plurality ofpixels to control the compensation duties thereof on a per pixel basis.13. The OLED of claim 11, wherein emission control lines of theplurality of gate lines are commonly, electrically connected to pixelson a same pixel line to control the compensation duties thereof on a perpixel line basis.
 14. The OLED of claim 1, wherein the luminance mapcontains information updated based on changes in electricalcharacteristics of the driving transistor and the OLED.
 15. The OLED ofclaim 1, wherein the luminance map contains information on a luminancedeviation resulting from difference in an amount of IR drop on a perpixel line basis.
 16. The OLED of claim 15, wherein the amount of IRdrop varies depending on a separation distance between a high potentialpower source and a corresponding pixel line.
 17. The OLED of claim 16,wherein as the separation distance increases, an amount of adjustment ofthe compensation gray levels or the compensation duties of pixels on thecorresponding pixel line increases.
 18. The OLED of claim 1, wherein thecompensation gray levels of the plurality of pixels or the compensationduties of the plurality of pixels are further adjusted by varying agamma power voltage applied to a data driver of the display paneldriver.
 19. The OLED of claim 1, wherein a high potential power voltageis set in an active region in a Vds-Ids plane of the driving transistor.20. The OLED of claim 1, wherein the timing controller time-divides aperiod of one frame into at least two driving sub-frames and acompensation sub-frame to increase a gray level representationperformance.